Conventional chips, as illustrated in FIG. 3, have their ground planes located at the bottom of the chip (opposite the contact pads) and the pads on the chip are located at the top of the chip. FIG. 3 illustrates an approach in the prior art, in which chip 100 rests on substrate 120 that, in turn, may be attached to a printed circuit board. Electrical connections for signals are made by wire bonding wires 115 from contacts on the top surface of the chip in the figure to pads on substrate 120. Surface 103, opposite to the contacts is the ground plane and is in thermal contact with substrate 120.
Generally when power amplifier integrated circuits are designed using a substrate carrier for the power amplifier integrated circuit, the substrate includes many via holes (thermal via holes) 140 located in the area where the power amplifier integrated circuit is to be mounted. These holes are placed to conduct heat away from the power amplifier integrated circuit and into the ambient. At higher frequencies (e.g. >2 GHz), the length of the via holes also plays an important role, since the via holes can create parasitic inductance in addition to the inductance created by the bondwires, thereby affecting the circuit's performance.
In addition, at these high frequencies, the bandwidth of the signal can be significantly reduced due to the parasitic inductance created by the bondwires at these frequencies. Further, the bondwires at DC voltage exhibit low resistance, thus reducing the power efficiency of a power amplifier integrated circuit.
Another problem with present technology is the bondwire bonding machinery. When bonding bondwires, the tolerance error for the length of the bondwires could be as much as 30%; i.e. the actual path 115 in FIG. 3 can be 30% greater than the direct path 116. Arrow 117 indicates a typical extra vertical dimension. Hence, at higher frequencies, it is more difficult for designers to design circuitry so that this 30% can be compensated.